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dual 8 - / 10 - / 12 - bit, high bandwidth , multipl ying dacs with serial interface data sheet ad5429 / ad5439 / ad5449 rev. e document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may re sult from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2004 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features 10 mhz multiplying bandwidth inl of 0.25 lsb @ 8 bits 16- lead tssop package 2.5 v to 5.5 v supply operation 10 v reference input 50 mhz serial interface 2.47 msps update rate extended temperature range : ?40c to +125c 4 - quadrant multiplication power - on reset 0.5 a typical current consumption guaranteed monotonic daisy - chain mode readback function a pplications portable battery - powered applications waveform generators analog processing instrumentation applications programmable amplifiers and atte nuators digitally controlled calibration programmable filters and oscillators composite video ultrasound gain, offset, and voltage trimming g eneral description the ad5429/ad5439/ad5449 1 are cmos, 8 - , 10 - , and 12 - bit, dual - channel, current output digital - t o - analog converters (dac) , respec tively. these devices operate from a 2.5 v to 5.5 v power supply, making them suited to battery - powered and other applications. as a result of being manufactured on a cmos submicron process, these parts offer excellent 4 - qu adrant multiplication character - istics, with large signal multiplying bandwidths of 10 mhz. the applied external reference input voltage (v ref ) determines the full - scale output current. an integrated feedback resistor (r fb ) provides temperature tracking an d full - scale voltage output when combined with an external current - to - voltage precision amplifier. these dacs use a double - buffered, 3 - wire serial interf ace that is compatible with spi , qspi?, microwire?, and most dsp interface standards. in addition, a se rial data out (sdo) pin allows daisy - chaining when multiple packages are used. data readback allows the user to read the contents of the dac register via the sdo pin. on power - up, the internal shift register and latches are filled with 0s, and the dac outp uts are at zero scale. the ad5429/ad5439/ad5449 dacs are available in 16 - lead tssop packages. the ev - ad5415/49sdz evaluation board is available for evaluating dac performanc e. for more information, see the ug - 297 evaluation board user guide. f unctional block diag ram sync ad5429/ad5439/ad5449 v ref b v ref a sclk sdin i out 1b i out 1a 8-/10-/12-bit r-2r dac a 8-/10-/12-bit r-2r dac b r fb a power-on reset dac register dac register rfb r rfb r i out 2a i out 2b ldac 04464-001 v dd clr r fb b input register input register shift register ldac sdo figure 1. 1 u.s. patent number 5,689,257.
ad5429/ad5439/ad5449 data sheet rev. e | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 5 timing diagrams .......................................................................... 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 14 theory of operation ...................................................................... 15 digital - to - analog converter .................................................... 15 circuit operation ....................................................................... 15 single - supply applications ....................................................... 17 adding gain ................................................................................ 18 divider or programmabl e gain element ................................ 18 reference selection .................................................................... 19 amplifier selection .................................................................... 19 serial interface ............................................................................ 20 microprocessor interfacing ....................................................... 22 pcb layout and power supply decoupling ........................... 24 overview of ad54xx devices ....................................................... 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 revision history 5/13 rev. d to rev. e changes to general description .................................................... 1 changes to ordering guide .......................................................... 26 6 /11 rev. c to rev. d changes to general description .................................................... 1 deleted evaluation board for the dac section ......................... 2 4 changes to ordering guide .......................................................... 30 4/10 rev. b to rev. c added to figure 4 ............................................................................. 6 3 /08 rev. a to rev. b added t 13 and t 14 parameters to table 2 ......................................... 5 changes to figure 2 .......................................................................... 5 changes to figure 3 .......................................................................... 6 changes to figure 38 ...................................................................... 16 changes to ordering guide .......................................................... 30 7/05 rev. 0 to rev. a changes to features list .................................................................. 1 changes to specificatio ns ................................................................ 3 changes to timing characteristics .................................................5 changes to absolute maximum ratings section ..........................7 changes to general description section .................................... 15 changes to table 5 .......................................................................... 15 changes to table 6 .......................................................................... 16 changes to single - supply applications section ......................... 17 c hanges to divider or programmable gain element section .... 18 changes to table 7 through table 10 ......................................... 20 added adsp - bf5xx - to - ad5429/ad5439/ad5449 interface section ........................................................................ 23 change to pcb layout and power supply decoupling section .......................................... 25 changes to power supplies for the evaluation board section .... 25 changes to table 13 ....................................................................... 29 updated outline dimensions ....................................................... 30 changes to ordering guide .......................................................... 30 7/04 revision 0: initial version
data sheet ad5429/ad5439/ad5449 rev. e | page 3 of 28 specifications v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v. temperature range for y version: ?40c to +125c. all specifications t min to t max , unless otherwise noted. dc performance is measured with the op177 , and ac performance is measured with the ad8038 , unless otherwise noted. table 1 . parameter 1 min typ max unit conditions static performance ad5429 resolution 8 bits relative accuracy 0.5 lsb differential nonlinearity 1 lsb guaranteed monotonic ad5439 resolution 10 bits relative accuracy 0.5 lsb differential nonlinearity 1 lsb guaranteed monotonic ad5449 resolution 12 bits relative accuracy 1 lsb differential nonlinearity ?1/+2 lsb guaranteed monotonic gain error 25 mv gain error temperature coefficient 5 ppm fsr/c output leakage current 5 na data = 0x0000, t a = 25c, i out 1 15 na data = 0x0000, i out 1 reference in put reference input range 10 v v ref a, v ref b input resistance 9 11 13 k? input resistance temperature coefficient = ?50 ppm/c v ref a -to - v ref b input resistance mismatch 1.6 2.5 % typ ical = 25c, max imum = 125c input capacitance c ode 0 3.5 pf code 4095 3.5 pf digital inputs/output input high voltage, v ih 1.7 v v dd = 3.6 v to 5.5 v 1.7 v v dd = 2.5 v to 3.6 v input low voltage, v il 0.8 v v dd = 2.7 v to 5.5 v 0.7 v v dd = 2.5 v to 2.7 v output high voltage, v oh v dd ? 1 v v dd = 4.5 v to 5.5 v, i source = 200 a v dd ? 0.5 v v dd = 2.5 v to 3.6 v, i source = 200 a output low voltage, v ol 0.4 v v dd = 4.5 v to 5.5 v, i sink = 200 a 0.4 v v dd = 2.5 v to 3.6 v, i sink = 200 a input leakage current, i il 1 a input capacitance 4 10 pf dynamic performance reference - multiplying bandwidth 10 mhz v ref = 3.5 v p - p, dac loaded all 1s output voltage settling time r load = 100 ? , c load = 15 pf, v ref = 10 v , dac latch alternately loaded with 0s and 1s m easured to 1 mv of fs 80 120 ns measured to 4 mv of fs 35 70 ns measured to 16 mv of fs 30 60 ns digital delay 20 40 ns digital -to - analog glitch impulse 3 nv - sec 1 lsb change around major carry, v ref = 0 v
ad5429/ad5439/ad5449 data sheet rev. e | page 4 of 28 parameter 1 min typ max unit conditions multiplying feedthroug h error dac latches loaded with all 0s, v ref = 3.5 v 70 db 1 mhz 48 db 10 mhz output capacitance 12 17 pf dac latches loaded with all 0s 25 30 pf dac latches loaded with all 1s digital feedthrough 3 5 nv - sec feedthrough to dac ou tput with cs high and alternate loading of all 0s and all 1s output noise spectral density 25 nv/hz @ 1 khz analog thd 81 db v ref = 3. 5 v p - p, all 1s loaded, f = 1 khz digital thd clock = 10 mhz, v ref = 3.5 v 100 khz f out 61 db 50 khz f out 66 db sfdr performance (wide band) ad5449, 65k codes, v ref = 3.5 v clock = 10 mhz 500 khz f out 55 db 100 khz f out 63 db 50 khz f out 65 db clock = 25 mhz 500 khz f out 50 db 100 khz f out 60 db 50 khz f out 62 db sfdr performance (narrow band) ad5449, 65k codes, v ref = 3.5 v clock = 10 mhz 500 khz f out 73 db 100 khz f out 80 db 50 khz f out 87 db clock = 25 mhz 500 khz f out 70 db 100 khz f out 75 db 50 khz f out 80 db intermodulation distortion ad5449, 65k codes, v ref = 3.5 v f 1 = 40 khz, f 2 = 50 khz 72 db clock = 10 mhz f 1 = 40 khz, f 2 = 50 khz 65 db clock = 25 mhz power requirements power supply range 2.5 5.5 v i dd 0.7 a t a = 25c, logic inputs = 0 v or v dd 0.5 10 a t a = ?40c to +125c, logic inputs = 0 v or v dd power supply sensitivity 0.001 %/% ? v dd = 5% 1 guaranteed by design and characterization, not subject to production test.
data sheet ad5429/ad5439/ad5449 rev. e | page 5 of 28 timing characteristi cs all input signals are specified with t r = t f = 1 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. v dd = 2.5 v to 5.5 v, v ref = 10 v, i out 2 = 0 v, temperature range for y version: ?40c to +125c. all specifications t min to t max , unless otherwise noted . table 2 . parameter 1 limit at t min , t max unit conditions/comments 2 f sclk 50 mhz max max imum clock frequency t 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 5 ns min data setup time t 6 4 ns min data hold time t 7 5 ns min sync rising edge to sclk falling edge t 8 30 ns min minimum sync high time t 9 0 ns min sclk falling edge to ldac falling edge t 10 12 n s min ldac pulse width t 11 10 ns min sclk falling edge to ldac rising edge t 12 3 25 ns min sclk active edge to sdo valid, strong sdo driver 60 ns min sclk active edge to sdo valid, weak sdo driver t 1 3 12 ns min clr pulse width t 1 4 4.5 ns min sync rising edge to ldac falling edge update rate 2.47 msps consists of cycle time, sync high time, data setup, and out put voltage settling time 1 guaranteed by design and characterization, not subject to production test. 2 falling or rising edge as determined by the control bits of the serial word. strong or weak sdo driv er selected via the control register. 3 daisy - chain and readback modes cannot operate at maximum clock frequency. sdo timing specifications are measured with a load circuit, as shown in figure 5 . timing diagrams t 1 t 2 t 3 t 7 t 8 t 4 t 5 t 6 t 9 t 10 t 1 1 db15 db0 sclk sdin ldac 1 ldac 2 sync 1 asynchronous ldac upd a te mode. 2 synchronous ldac upd a te mode. notes 1. alternatively, data can be clocked into the input shift register on the rising edge of sclk as determined by the control bits. timing is as above, with sclk inverted. 04464-002 figure 2 . standalone mode timing diagram
ad5429/ad5439/ad5449 data sheet rev. e | page 6 of 28 04464-003 t 8 t 7 t 12 t 1 t 3 t 2 t 4 t 5 t 6 db15 (n) db15 (n + 1) db0 (n) db0 (n + 1) db15 (n) db0 (n) sclk sync sdin sdo notes 1. alternatively, data can be clocked into the input shift register on the rising edge of sclk as determined by the control bits. in this case, data would be clocked out of sdo on the falling edge of sclk. timing is as above, with sclk inverted. figure 3. daisy - chain timing diagram sdo sdin sync sclk 16 32 db15 db0 db15 db0 db15 undefined nop condition db0 input word specifies register to be read selected register data clocked out 04464-059 figure 4. readback mode timing diagram 200 a i ol 200 a i oh to output pin c l 50pf v oh (min) + v ol (max) 2 04464-004 figure 5 . load circuit for sdo timing specifications
data sheet ad5429/ad5439/ad5449 rev. e | page 7 of 28 absolute maximum rat ings transient currents of up to 100 ma do not cause scr latch - up. t a = 25 c, unless otherwise noted. table 3 . parameter rating v dd to gnd ? 0.3 v to +7 v v ref x , r fb x to gnd ? 12 v to +12 v i out 1, i out 2 to gnd ? 0.3 v to +7 v input current to any pin except supplies 10 ma logic inputs and output 1 ? 0.3 v to v dd + 0.3 v operating temperature range extended (y version) ?40c to +125c stor age temperature range ? 65c to +150c junction temperature 150c 16- lead tssop, ja thermal impedance 150c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 235c 1 overvoltages at sclk, sync , and sdin are cla mped by internal diodes. stresses above those listed under absolute maximum ra tings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. esd caution
ad5429/ad5439/ad5449 data sheet rev. e | page 8 of 28 pin configuration an d function descripti ons 1 2 3 4 5 6 7 8 nc = no connect 16 1 5 1 4 1 3 1 2 1 1 1 0 9 i out 2a r fb a v ref a sclk ldac gnd i out 1a i out 2b r fb b v ref b sync sdin sdo clr v dd i out 1b ad5429/ ad5439/ ad5449 top view (not to scale) 04464-005 figure 6 . pin config uration table 4 . pin function descriptions pin no. mnemonic description 1 i out 1a dac a current output. 2 i out 2a dac a analog ground. this pin should typically be tied to the analog ground of the system, but it can be biase d to achieve single - supply operation. 3 r fb a dac feedback resistor pin. this pin establishes voltage output for the dac by connecting to an external amplifier output. 4 v ref a dac a reference voltage input pin. 5 gnd ground pin. 6 ldac load dac input. this pin allows asynchronous or synchronous updates to the dac output. the dac is asynchronously updated when this signal goes low. alternatively, if this line is held permanently low, an automatic or synchronous update mode is selected, whereby the dac is updated on the 16th clock falling edge when the device is in standalone mode, or on the rising edge of sync when in daisy - chain mode. 7 sclk serial clock input. by default, data is clocked into the input shift register on the falling edge of the serial clock input. alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register on the rising edge of sclk. 8 sdin serial data input. data is clocked into the 16 - bit input register on the active edge of the serial clock input. by default, data is clocked at power - on into the shift register on the falling edge of sclk. the control bits allow the user to change the active edge to a rising edge. 9 sdo serial data output. this pin allows a number of parts to be daisy - chained. by default, data is clocked into the shift register on the falling edge and clocked out via sdo on the rising edge of sclk. data is always clocked out on the alterna te edge to loading data to the shift register. writing the readback control word to the shift register makes the dac register contents available for readback on the sdo pin, and they are clocked out on the next 16 opposite clock edges to the active clock e dge. 10 sync active low control input. this pin provides the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers, and the input shift register is enabled . data is loaded into the shift register on the active edge of the subsequent clocks. in standalone mode, the serial interface counts the clocks, and data is latched into the shift register on the 16th active clock edge. 11 clr act ive low control input. this pin clears the dac output, input, and dac registers. configuration mode allows the user to enable the hardware clr pin as a clear - to - zero scale or midscale , as required. 12 v dd positive power supply inp ut. these parts can be operated from a supply of 2.5 v to 5.5 v. 13 v ref b dac b reference voltage input pin. 14 r fb b dac b feedback resistor pin. this pin establishes voltage output for the dac by connecting to an external amplifier output. 15 i o ut 2b dac b analog ground. this pin typically should be tied to the analog ground of the system, but it can be biased to achieve single - supply operation. 16 i out 1b dac b current output.
data sheet ad5429/ad5439/ad5449 rev. e | page 9 of 28 typical performance characteristics ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 inl (lsb) 0.10 0.15 0.20 04464-017 0 50 100 150 200 250 code t a = 25c v ref = 10v v dd = 5v figure 7 . inl vs. code (8 - bit dac) ? 0.5 ? 0.4 ? 0.3 ? 0.2 ? 0.1 0 0.1 0.2 0.3 0.4 0.5 inl (lsb) 04464-018 0 200 400 600 800 1000 code t a = 25 c v ref = 10v v dd = 5v figure 8 . inl vs. code (10 - bit dac) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 inl (lsb) 2 0 0 0 1 5 0 0 5 0 0 1 0 0 0 0 2 5 0 0 3 0 0 0 3 5 0 0 4 0 0 0 code 04464-019 t a = 25c v ref = 10v v dd = 5v figure 9 . inl vs. code (12 - bit dac) ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 dnl (lsb) 0.10 0.15 0.20 04464-020 0 50 100 150 200 250 code t a = 25c v ref = 10v v dd = 5v figure 10 . dnl vs. code (8 - bit dac) ? 0.5 ? 0.4 ? 0.3 ? 0.2 ? 0.1 0 0.1 0.2 0.3 0.4 0.5 dnl (lsb) 04464-021 0 200 400 600 800 1000 code t a = 25 c v ref = 10v v dd = 5v figure 11 . dnl vs. code (10 - bit dac) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 dnl (lsb) 2 0 0 0 1 5 0 0 5 0 0 1 0 0 0 0 2 5 0 0 3 0 0 0 3 5 0 0 4 0 0 0 code 04464-022 t a = 25c v ref = 10v v dd = 5v figure 12 . dnl vs. code (12 - bit dac)
ad5429/ad5439/ad5449 data sheet rev. e | page 10 of 28 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 inl (lsb) 65 34 2 78910 reference voltage 04464-035 max inl min inl t a = 25c v dd = 5v figure 13. inl vs. reference voltage ?0.70 ?0.65 ?0.60 ?0.55 ?0.50 ?0.45 ?0.40 dnl (lsb) 65 34 278910 reference voltage 04464-036 min dnl t a = 25c v dd = 5v figure 14. dnl vs. reference voltage ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 gain error (mv) ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) 04464-037 v dd = 5v v dd = 2.5v v ref = 10v figure 15. gain error vs. temperature input voltage (v) supply current (ma) 8 5 0 5.0 7 6 3 1 4 2 4.5 4.03.53.02.52.01.5 1.0 0.5 0 v dd = 5v v dd = 3v v dd = 2.5v 04464-038 t a = 25c figure 16. supply current vs. logic input voltage 0 0.2 0.4 0.6 0.8 1.0 i out 1 leakage (na) 1.2 1.4 1.6 4020 ?20 0 ?40 60 80 100 120 temperature (c) 04464-039 i out 1 v dd = 5v i out 1 v dd = 3v figure 17. i out 1 leakage current vs. temperature 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 supply current ( a) ?60 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) 04464-040 v dd = 5v v dd = 2.5v all 0s all 1s all 0s all 1s figure 18. supply current vs. temperature
data sheet ad5429/ad5439/ad5449 rev. e | page 11 of 28 0 2 4 6 8 10 12 14 i dd (ma) 1 0 k 1 k 1 0 1 0 0 1 1 0 0 k 1 m 1 0 m 1 0 0 m frequency (hz) 04464-041 t a = 25c loading zs to fs v dd = 5v v dd = 3v v dd = 2.5v figure 19 . supply current vs. update rate ?102 ?66 ?54 ?42 ?30 ?18 ?6 6 1 100 1k 10k 100k 1m 10m 100m frequenc y (hz) gain (db) t a = 25 c loading zs t o fs 0 ?60 ?48 ?36 ?24 ?12 ?84 ?72 ?78 ?90 ?96 t a = 25c v dd = 5v v ref = 3.5v c comp = 1.8pf am p = ad8038 al l on db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 al l off 04464-042 10 figure 20 . reference multiplying bandwidth vs. frequency and code ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 gain (db) 1 0 k 1 k 1 0 1 0 0 1 1 0 0 k 1 m 1 0 m 1 0 0 m frequency (hz) 04464-043 t a = 25 c v dd = 5v v ref = 3.5v c comp = 1.8pf amp = ad8038 figure 21 . reference multiplying bandwi dth all 1s loaded ?9 ?6 ?3 0 3 10k 100k 1m 10m 100m frequenc y (hz) t a = 25 c v dd = 5v gain (db) 04464-044 v ref = 2 v , ad8038 c c 1.47pf v ref = 2 v , ad8038 c c 1pf v ref = 0.15 v , ad8038 c c 1pf v ref = 0.15 v , ad8038 c c 1.47pf v ref = 3.51 v , ad8038 c c 1.8pf figure 22 . reference multiplying bandwidth vs. frequency and compensation capacitor ? 0.010 ? 0.005 0.005 0.025 0.035 0.045 0.015 0 0.020 0.030 0.040 0.010 output voltage (v) 0 20 40 60 80 100 120 140 160 180 200 time (ns) 04464-045 t a = 25c v ref = 0v amp = ad8038 c comp = 1.8pf 0x7ff to 0x800 0x800 to 0x7ff v dd = 5v v dd = 3v v dd = 3v v dd = 5v figure 23 . midscale transition, v ref = 0 v output voltage (v) 0 20 40 60 80 100 120 140 160 180 200 time (ns) 04464-046 ?1.77 ?1.76 ?1.75 ?1.74 ?1.73 ?1.72 ?1.71 ?1.70 ?1.69 ?1.68 0x7ff to 0x800 0x800 to 0x7ff v dd = 5v v dd = 3v v dd = 3v v dd = 5v t a = 25c v ref = 3.5v amp = ad8038 c comp = 1.8pf figure 24 . midscale tra nsition, v ref = 3.5 v
ad5429/ad5439/ad5449 data sheet rev. e | page 12 of 28 ? 120 ? 100 ? 80 ? 60 0 20 1 100 1k 10k 100k 1m 10m frequency (hz) ? 40 ? 20 t a = 25 c v dd = 3v amp = ad8038 full scale zero scale psrr (db) 04464-047 10 figure 25 . power supply rejection ratio vs. frequency ? 90 ? 85 ? 80 ? 75 ? 70 ? 65 ? 60 thd + n (db) 100 1k 1 10 10k 100k 1m frequency (hz) 04464-048 t a = 25 c v dd = 3v v ref = 3.5v p-p figure 26 . thd + noise vs. frequency 0 20 40 60 80 100 sfdr (db) 0 20 40 60 80 100 120 140 160 180 200 f out (khz) 04464-049 t a = 25 c v ref = 3.5v amp = ad8038 mclk = 1mhz mclk = 200khz mclk = 0.5mhz figure 27 . wideband sfdr vs. f out frequency 0 10 20 30 40 50 60 70 80 90 sfdr (db) 0 100 200 300 400 500 600 700 800 900 1000 f out (khz) 04464-050 mclk = 5mhz mclk = 10mhz mclk = 25mhz t a = 25c v ref = 3.5v amp = ad8038 figure 28 . wideband sfdr vs. f out frequency 04464-051 ? 90 ? 70 ? 50 ? 30 ? 10 sfdr (db) 0 frequency (mhz) ? 80 ? 60 ? 40 ? 20 0 t a = 25 c v dd = 5v amp = ad8038 65k codes 2 4 6 8 10 12 figure 29 . wideband sfdr, f out = 100 khz, clock = 25 mhz ? 04464-052 ? 100 ? 70 ? 50 ? 30 ? 10 sfdr (db) 0 frequency (mhz) ? 80 ? 60 ? 40 ? 20 0 t a = 25 c v dd = 5v amp = ad8038 65k codes 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 ? 90 figure 30 . wideband sfdr, f out = 500 khz, clock = 10 mhz
data sheet ad5429/ad5439/ad5449 rev. e | page 13 of 28 04464-053 ? 90 ? 70 ? 50 ? 30 ? 10 sfdr (db) 0 frequency (mhz) ? 80 ? 60 ? 40 ? 20 0 0.5 1.5 3.0 3.5 4.0 1.0 2.0 2.5 4.5 5.0 t a = 25 c v dd = 5v amp = ad8038 65k codes figure 31 . wideband sfdr, f out = 50 khz, clock = 10 mhz 04464-054 frequency (khz) ? t a = 25 c v dd = 3v amp = ad8038 65k codes ? 100 ? 70 ? 50 ? 30 ? 10 sfdr (db) 250 750 300 350 400 650 700 ? 80 ? 60 ? 40 ? 20 0 ? 90 450 500 550 600 figure 32 . narrow - band spectral response, f out = 500 khz, clock = 25 mhz 04464-055 ? 120 ? 60 ? 20 sfdr (db) 50 150 frequency (khz) 60 70 80 130 140 ? 80 ? 40 0 20 ? 100 90 100 110 120 ? t a = 25 c v dd = 3v amp = ad8038 65k codes figure 33 . narrow - band sfdr, f out = 100 khz, clock = 25 mhz 04464-056 frequency (khz) ? 100 ? 70 ? 50 ? 30 ? 10 imd (db) 70 120 75 80 85 115 ? 80 ? 60 ? 40 ? 20 0 ? 90 90 100 105 110 ? t a = 25 c v dd = 3v amp = ad8038 65k codes 95 figure 34 . narrow - band imd, f out = 90 khz, 100 khz, clock = 10 mhz 04464-057 ? 100 ? 40 ? 20 imd (db) ? 50 ? 30 ? 10 ? 90 ? 60 ? 70 ? 80 0 400 frequency (khz) 50 300 350 100 150 200 250 0 ? t a = 25 c v dd = 5v amp = ad8038 65k codes figure 35 . wideband imd, f out = 90 khz, 100 khz, clock = 25 mhz 100 1k 10k 100k frequency (hz) t a = 25 c amp = ad8038 full scale loaded to dac zero scale loaded to dac 04464-058 0 50 100 150 200 250 300 output noise (nv/ hz) midscale loaded to dac figure 36 . output noise spectral density
ad5429/ad5439/ad5449 data sheet rev. e | page 14 of 28 terminology relative accuracy (endpoint nonlinearity) a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero and full scale and is typically expressed in lsbs or as a percentage of the full - scale reading. differential nonlinearity the difference in the measured change and the ideal 1 lsb change between two adjacent codes. a specified differential nonlinearity of ?1 lsb maximum over the operating temperature range ensures monotonicity. gain error (full - scale error) a measure of the output error between an ideal dac and the actual device output. for these dacs, ideal maximum output is v ref ? 1 lsb. the gain error of the dacs is adjustable to zero with an external resistance. output leakage current the current that flows into the dac ladder switches when they are turned off. for the i out 1 x terminal, it can be measured by loading all 0s to the dac and measuring the i ou t 1 current. minimum current flows into the i out 2 x line when the dac is loaded with all 1s. output capacitance capacitance from i out 1 or i out 2 to agnd. output current settling time the amount of time for the output to settle to a specified level for a full - scale input change. for these devices, it is specified with a 100 ? resistor to ground. digital -to - analog glitch impulse the amount of charge injected from the digital inputs to the analog output when the inputs change state. this is normally specified as the area of the glitch in either pa - sec or nv - sec, depending on whether the glitch is measured as a current or voltage signal. digital feedthrough when the device is not selected, high frequency logic activity on the digital inputs of the device is capacit ively coupled through the device and produces noise on the i out pins and, subsequently, on the circuitry that follows . this noise is digital feedthrough. multiplying feedthrough error the error due to capacitive feedthrough from the dac reference input to the dac i out 1 x terminal when all 0s are loaded to the dac. digital crosstalk the glitch impulse transferred to the outputs of one dac in response to a full - scale code change (all 0s to all 1s, or vice versa) in the input register of the other dac. it is e xpressed in nv - sec. analog crosstalk the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full - scale code change (all 0s to all 1s, or vice versa) while keeping ldac high and then pulsing ldac low and monitoring the output of the dac whose digital code has not changed. the area of the glitch is expressed in nv - sec. channel -to - channel isolation the portion of input signal from the reference input of a dac that appears at the output of another dac. it is expressed in db. total harmonic distortion (thd) the dac is driven by an ac reference. the ratio of the rms sum of the harmonics of the dac output to the fu ndamental value is the thd. usually only the lower - order harmonics are included, such as the second to fifth harmonics. 1 5 4 3 2 v v v v v thd 2 2 2 2 log 20 + + + = intermodulation distortion (imd) the dac is driven by two co mbined sine wave references of frequency fa and freq uency fb. distortion pr oducts are produced at sum and difference freq uencies of mfa nfb, where m, n = 0, 1, 2, 3 intermodulation terms are those for which m or n is not equal to 0. the second - order terms include (fa + fb) and (fa ? fb), and the third - order terms are (2fa + fb), (2fa ? fb), (f + 2fa + 2fb) , and (fa ? 2fb). imd is defined as l fundamenta the of amplitude rms products distortion diff and sum the of sum rms imd log 20 = compliance voltage range the maximum range of (output) terminal voltage for which the device provides the specified characteristics.
data sheet ad5429/ad5439/ad5449 rev. e | page 15 of 28 theory of operation digital-to-analog converter the ad5429/ad5439/ad5449 are 8-, 10-, and 12-bit, dual- channel, current output dacs consisting of a standard inverting r-2r ladder configuration. figure 37 shows a simplified diagram for a single channel of the ad5449. the feedback resistor, r fb a, has a value of r. the value of r is typically 10 k (with a minimum of 8 k and a maximum of 12 k). if i out 1a and i out 2a are kept at the same potential, a constant current flows into each ladder leg, regardless of digital input code. therefore, the input resistance presented at v ref a is always constant. 2r s1 2r s2 2r s3 2r s12 2r dac data latches and drivers r r fb a i out 1a i out 2a v ref a 04464-006 rr r figure 37. simp lified ladder access is provided to the v ref x, r fb x, i out 1x, and i out 2x termi- nals of the dacs, making the devices extremely versatile and allowing them to be configured in several operating modes, such as unipolar mode, bipolar output mode, or single-supply mode. circuit operation unipolar mode using a single op amp, these devices can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in figure 38. when an output amplifier is connected in unipolar mode, the output voltage is given by n ref out dvv 2/ ??? where: d is the fractional representation of the digital word loaded to the dac. d = 0 to 255 (ad5429) = 0 to 1023 (ad5439) = 0 to 4095 (ad5449) n is the number of bits. with a fixed 10 v reference, the circuit shown in figure 38 gives a unipolar 0 v to ?10 v output voltage swing. when v in is an ac signal, the circuit performs 2-quadrant multiplication. table 5 shows the relationship between digital code and the expected output voltage for unipolar operation using the 8-bit ad5429 dac. table 5. unipolar code table digital input analog output (v) 1111 1111 ?v ref (255/256) 1000 0000 ?v ref (128/256) = ?v ref /2 0000 0001 ?v ref (1/256) 0000 0000 ?v ref (0/256) = 0 ad5429/ ad5439/ ad5449 04464-007 notes 1. r1 and r2 used only if gain adjustment is required. 2. c1 phase compensation (1pf to 2pf) may be required 3. dac b omitted for clarity. i out 1a i out 2a v ref x v dd c1 a1 v out = 0v to ?v ref agnd r2 v dd v ref sdin gnd sclk sync r fb a r1 if a1 is a high speed amplifier. microcontroller figure 38. unipolar operation
ad5429/ad5439/ad5449 data sheet rev. e | page 16 of 28 bipolar operation in some applications, it m ay be necessary to generate full 4 - quadrant multiplying operation or a bipolar output swing. this can easily be accomplished by using another external amplifier and three external resi stors, as shown in figure 39. when v in is an ac signal, the circuit performs 4 - quadrant multiplication. when connected in bipolar mode, the output voltage is ( ) ref n ref out v d v v / = / 1 2 / where: d is the fractional representation of t he digital word loaded to the dac. d = 0 to 255 (ad5429) = 0 to 1023 (ad5439) = 0 to 4095 (ad5449) n is the number of bits. table 6 shows the relationship between digital code and the expected output voltage for bipolar operation with the ad5429. table 6 . bipolar code digital input analog output (v) 1111 1111 +v ref (255/256) 1000 0000 0 0000 0001 ?v ref (255/256) 0000 0000 ?v ref (256/256) stability in the i - to - v configuration, the i out of the dac and the inverting node of the op amp must be connected as closely as possible, and proper pcb layout techniques must be used. because every code cha nge corresponds to a step function, gain peaking may occur if the op amp has limited gain bandwidth product (gbp) and there is excessive parasitic capacitance at the inverting node. this parasitic capacitance introduces a pole into the open - loop response, which can cause ringing or instability in the closed - loop applications circuit. as shown in figure 38 and figure 39 , an optional compensation capacitor, c1, can be added in parallel with r fb x for stabil ity. too small a value of c1 can produce ringing at the output, whereas too large a value can adversely affect the settling time. c1 should be found empirically, but 1 pf to 2 pf is generally adequate for the compensation. 04464-008 i out 1a i out 2a ad5429/ ad5439/ ad5449 v ref x v dd c1 a1 v out = ?v ref to +v ref r2 v dd v ref 10v sdin sclk sync microcontroller a2 r4 10k? r5 20k? notes 1. r1 and r2 used only if gain adjustment is required. 2. matching and tracking is essential for resistor pairs 3. c1 phase compensation (1pf to 2pf) may be required 4. dac b and additional pins omitted for clarity. if a1/a2 is a high speed amplifier. adjust r1 for v out = 0v with code 10000000 loaded to dac. r3 and r4. r3 20k? r1 r fb a agnd gnd r1 figure 39 . bipolar operation
data sheet ad5429/ad5439/ad5449 rev. e | page 17 of 28 single - supply applications voltage - switching mode figure 40 shows the dacs operating in voltage - switching mode. the reference voltage, v in , is applied to the i out 1a pin; i out 2a is connected to agnd; a nd the output voltage is available at the v ref a terminal. in this configuration, a positive reference voltage results in a positive output voltage, making single - supply operation possible. the output from the dac is voltage at a constant imped ance (the dac ladder resistance). therefore, an op amp is necessary to buffer the output voltage. the reference input no longer sees a constant input impedance ; instead, it sees one that varies with code. therefore, the voltage input should be driven from a low imped ance source. note that v in is limited to low voltages because the switches in the dac ladder no longer have the same source - drain drive voltage. as a result, their on resistance differs and degrades the integral linearity of the dac. also, v in must not g o negative by more than 0.3 v, or an internal diode turns on, causing the device to exceed the maximum ratings. in this type of application, the full range of multiplying capability of the dac is lost. positive output voltage the output voltage polarity is opposite to the v ref polarity for dc reference voltages. to achieve a positive voltage output, an applied negative reference to the input of the dac is preferred over the output inversion through an inverting amplifier because of the resistor tolerance e rrors. to generate a negative reference, the reference can be level - shifted by an op amp such that the v out and gnd pins of the reference become the virtual ground and ?2.5 v, respectively, as shown in figure 41. v out v dd gnd v in i out 2 a i out 1 a r fb a v dd v ref a r2 r1 04464-009 notes 1. additiona l pins omitted for clarit y . 2. c1 phase compens a tion (1pf t o 2pf) m a y be required if a1 is a high speed amplifier. 8-/10-/12-bit dac figure 40 . single - supply voltage - switching mode v out = 0v to +2.5v v dd = +5v gnd i out 2a i out 1a r fb a v dd v ref a c 1 gnd v in v out adr03 + 5v ? 5v 8-/10-/12-bit dac ? 2.5v 04464-010 notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required if a1 is a high speed amplifier. figure 41 . positive voltage output with minimum components
ad5429/ad5439/ad5449 data sheet rev. e | page 18 of 28 adding gain in appl ications in which the output voltage must be greater than v in , gain can be added with an additional external amplifier, or it can be achieved in a single stage. consider the effect of temper - ature coefficients of the thin film resistors of the dac. simply placing a resistor in series with the rfb resistor causes mismatches in the temperature coefficients, resulting in larger gain temper - ature coefficient errors. instead, the circuit in figure 42 shows the recommended method of inc reasing the gain of the circuit. r1, r2, and r3 should have similar temperature coefficients, but they need not match the temperature coefficients of the dac. this approach is recommended in circuits in which gains of greater than 1 are required. divider or programmable gain element current - steering dacs are very flexible and lend themselves to many applications. if this type of dac is connected as the feedback element of an op amp and r fb a is used as the input resistor, as shown in figure 43 , the output voltage is inversely proportional to the digital input fraction, d. for d = 1 ? 2 ?n , the output voltage is ( ) n in in out v d v v / / / = / = 2 1 / / as d is reduced, the output voltage increases. for smal l values of the digital f raction d, it i s important to ensure that the ampli fier does not saturate and the required accuracy is met. for example, an 8 - bit d ac driven with binary code of 0x10 (0001 0000) that is, 16 decimal in the circuit of figure 43 should cause the o utput voltage to be 16 v in . however, if the dac has a linearity speci - fication of 0.5 lsb, d can have a weight in the range of 15.5/256 to 16.5/256 , so that the possible output voltage is in the range of 15.5 v in to 16.5 v in . this range represents an er ror of 3%, even though the dac itself has a maximum error of 0.2%. dac leakage current is also a potential error source in divider circuits. the leakage current must be counterbalanced by an opposite current supplied from the op amp through the dac. becau se only a fraction, d, of the current into the v ref x terminal is routed to the i out 1 terminal, the out put voltage changes as follows: output error voltage due to dac leakage = (leakage r)/d where r is the dac resistance at the v ref x terminal. for a dac l eakage current of 10 na, r = 10 k?, and a gain (that is, 1/d) of 16, the error voltage is 1.6 mv. v dd r fb a i out 1a i out 2a c1 gnd v dd v ref a notes 1. additional pins omitted for clarity. 2. c1 phase compensation (1pf to 2pf) may be required 8-/10-/12-bit dac v in r1 r3 r2 v out r1 = r2r3 r2 + r3 gain = r2 + r3 r2 04464-011 if a1 is a high speed amplifier. figure 42 . increasing gain of current output dac v in notes 1. additiona l pins omitted for clarit y . v ref a v dd v dd r fb a i out 1 a i out 2 a gnd v out 04464-012 8-/10-/12-bit dac figure 43 . current - steering dac used as a divider or programmable gain element
data sheet ad5429/ad5439/ad5449 rev. e | page 19 of 28 reference selection when selecting a reference for use with the ad54xx series of current output dacs, pay attention to the reference output voltage temperature coefficient specification. this parameter affects not only the ful l - scale error, but it can also affect the linearity (inl and dnl) pe rformance. the reference temper ature coefficient should be consistent with the system accuracy specifications. for example, an 8 - bit system required to hold its overall specification to wi thin 1 lsb over the temperature range of 0c to 50c dictates that the maximum system drift with temperature should be less than 78 ppm/c. a 12 - bit system with the same temperature range to overall specification within 2 lsbs requires a maximum drift of 10 ppm/c. by choosing a precision reference with a low output temperature coefficient, this error source can be minimized. table 7 lists some references available from analog devices , inc., that are suitable for use with this range of current output dacs. amplifier selection the primary requirement for the current - steering mode is an amplifier with low input bias currents and low input offset voltage. because of the code - dependent output resistance of the dac, the input offset voltage of an op amp is multiplied by the variable gain of the circuit. a change in this noise gain between two adjacent digital fractions produces a step change in the outpu t voltage due to the amplifier in put offset voltage. this output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, could cause the dac to be non - monotonic. the input bias current of an op amp also generates an offset at the vol tage output as a result of the bias current flowing in the feedback resistor, r fb . most op amps have input bias currents low enough to prevent significant errors in 12 - bit applications. common - mode rejection of the op amp is importan t in voltage - switching circuits because it produces a code - dependent error at the volta ge output of the circuit. most op amps have adequate co mmon - mode rejection for use at 8 - , 10 - , and 12 - bit resolution. if the d ac switches are driven from true wideband low impedance sources (v in and agnd), they settle quickly. consequently, the slew rate and settling time of a voltage - switching dac circuit is de termined largely by the output op amp. to obtain minimum settling time in this configuration, minimize capacitance at the v ref node (t he voltage output node in this application) of the dac by using low input capacitance buffer amplifiers and careful board design. most single - supply circuits include ground as part of the analog signal range, which , in turn , requires an amplifier that can handle rail - to - rail signals. analog devices offers a wide range of single - supply amplifiers (see table 8 and table 9 ) . table 7 . suitable a nalog devices precision references part no. output voltage (v) initial tolerance (%) temp drift (ppm/c) i ss (ma) output noise (v p - p) package adr01 10 0.05 3 1 20 soic -8 adr01 10 0.05 9 1 20 tsot - 23, sc70 adr02 5 0.06 3 1 10 soic -8 adr02 5 0.06 9 1 10 tsot - 23, sc70 adr03 2.5 0.10 3 1 6 s oic -8 adr03 2.5 0.10 9 1 6 tsot - 23, sc70 adr06 3 0.10 3 1 10 soic -8 adr06 3 0.10 9 1 10 tsot - 23, sc70 adr431 2.5 0.04 3 0.8 3.5 soic - 8 adr435 5 0.04 3 0.8 8 soic -8 adr391 2.5 0.16 9 0.12 5 tsot -23 adr395 5 0.10 9 0.12 8 tsot -23 table 8 . suitable analog devices precision op amps part no. supply voltage (v) v os (max) (v) i b (max) (na) 0.1 hz to 10 hz noise ( v p - p) supply current (a) package op97 2 to 20 25 0.1 0.5 600 soic - 8 op1177 2.5 to 15 60 2 0.4 500 m s o p, s oic - 8 ad8551 2.7 to 5 5 0.05 1 975 msop, soic - 8 ad8603 1.8 to 6 50 0.001 2.3 50 tsot ad8628 2.7 to 6 5 0.1 0.5 850 tsot, soic - 8 table 9 . suitable analog devices high speed op amps part no. supply voltage (v) bw @ acl (mhz) sl ew rate (v/s) vos (max) (v) i b (max) (na) package ad8065 5 to 24 145 180 1 500 6 000 soic - 8, sot - 23, msop ad8021 2.5 to 12 490 120 1 000 10,500 soic - 8, msop ad8038 3 to 12 350 425 3 000 750 soic - 8, sc70-5 ad9631 3 to 6 320 1 300 10,000 7 000 soic -8
ad5429/ad5439/ad5449 data sheet rev. e | page 20 of 28 serial interface the ad 5429/ad5439/ad5449 have an easy - to - use , 3 - wire interface that is compatible with spi, qspi, microwire, and most dsp interface standards. data is written to the device in 16- bit words. each 16 - bit word consists of four control bit s and eight, 10, or 12 data bits, as shown in figure 44 through figure 46. low power serial interface to minimize the power consumption of the device, the interface powers up fully only when the devic e is being written to, that is, on the falling edge of sync . the sclk and s din input buffers are powered down on the rising edge of sync . dac control bit c3 to control bit c0 control bit c3 to control bit c0 al low c ontrol of various functions of the dac, as shown in table 11 . the default settings of the dac at power - on are such that data is clocked into the shift register on falling clock edges and daisy - chain mode is enabled. the dev ice powers on with a zero - scale load to the dac register and i out lines. the dac control bits allow the user to adjust certain features at power - on. for example, daisy - chaining can be disabled if not in use, an active clock edge can be changed to a rising edge, and dac output can be cleared to either zero scale or midscale. the user can also initiate a readback of the dac register contents for veri - fication. control register (control bits = 1101) while maintaining software compatibility with single - channel current output dacs ( ad5426/ad5432/ad5443 ), these dacs also feature additional interface functionality. set the control bits to 1101 to enter control register mode. figure 47 shows th e contents of the control register, the functions of which are described in the following sections. sdo control (sdo1 and sdo2) the sdo bits enable the user to control the sdo output driver strength, disable the sdo output, or configure it as an open - drai n driver. the strength of the sdo driver affects the timing of t 12 , and, when stronger, allows a faster clock cycle. table 10 . sdo control bits sdo2 sdo1 function implemented 0 0 full sdo driver 0 1 weak sdo driver 1 0 sdo configured as open drain 1 1 disable sdo output daisy - chain control (dsy) dsy allows the enabling or disabling of daisy - chain mode. a 1 enables daisy - chain mode; a 0 disables daisy - chain mode. when disabled, a readback request is accepted; sdo is auto - matically enabled; the dac register contents of the rele vant dac are clocked out on sdo; and, when complete, sdo is disabled again. hardware clr bit (hclr) the default setting for the hardware clr bit is to clear the registers and dac output to zero code. a 1 in the hclr bit allows the clr pin to clear th e dac outputs to midscale, and a 0 clears to zero scale. active clock edge (sclk) the default active clock edge is a falling edge. write a 1 to this bit to clock data in on the rising edge, or a 0 to clock it in on the falling edge. d at a bits contro l bits c3 c2 c1 c0 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 db0 (lsb) db15 (msb) 04464-013 figure 44 . ad5429 8 - bit input shift register contents d at a bits contro l bits c3 c2 c1 c0 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 db0 (lsb) db15 (msb) 04464-014 figure 45 . ad5439 10 - bit input shift regist er contents d at a bits contro l bits c3 c2 c1 c0 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db0 (lsb) db15 (msb) 04464-015 figure 46 . ad5449 12 - bit input shift register contents contro l bits 1 1 0 1 sdo2 sdo1 ds y hclr sclk x x x x x x x db0 (lsb) db15 (msb) 04464-016 figure 47 . control register loading sequence
data sheet ad5429/ad5439/ad5449 rev. e | page 21 of 28 sync function sync is an edge - triggered i nput that acts as a frame synchron - ization signal and chip enable. data can be transferred into the device only while sync is low. to start the serial data transfer, sync should be taken low, observing the mini mum sync falling edge to sclk falling edge setup time, t 4 . daisy - chain mode daisy - chain mode is the default power - on mode. to disable the daisy - chain function, write 1001 to the control word. in daisy - chain mode, the internal gating on sclk is disabled. sclk is continuously applied to the input shift register when sync is low. if more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked ou t on the rising ed ge of sclk (this is the default; use the control word to change the active edge) and is valid for the next device on the falling edge of sclk (default). by connecting this line to the sdin input on the next device in the chain, a multide vice interface is constructed. for each device in the system, 16 clock pulses are required. therefore, the total number of clock cycles must equal 16 n, where n is the total number of devices in the chain. see figure 4 . when the s erial transfer to all devices is complete, sync should be taken high. this prevents additional data from being clocked into the input shift register. a burst clock containing the exact number of clock cycles can be used, after which sync can be taken high. after the rising edge of sync , data is automatically transferred from the input shift register of each device to the addressed dac. when control bits = 0000, the device is in no operati on mode. this may be useful in daisy - chain applications in which the user does not want to change the settings of a particular dac in the chain. write 0000 to t he control bits for that dac; subsequent data bits are ignored. standalone mode after power - on, write 1001 to the control word to disable daisy - chain mode. the first falling edge of sync resets the serial clock counter to ensure that the correct number of bits are shifted in and out of the serial shift registers. a sync edge during the 16 - bit write cycle causes the device to abort the current write cycle. after the falling edge of the 16th sclk pulse, data is automat - ically transferred from the input shift register to the dac. for another serial transfer t o take place, the counter must be reset by the falling edge of sync . ldac function the ldac function allows asynchronous and synchronous updates to the dac output. the dac is asynchronou sly updated when this signal goes low. alternatively, if this line is held perma - nently low, an automatic or synchronous update mode is selected, whereby the dac is updated on the 16th clock falling edge when the device is in standalone mode, or on the ris ing edge of sync when the device is in daisy - chain mode. software ldac function load - and - update mode can also serve as a software update func - tion, irrespective of the voltage level on the l dac pin. table 11 . dac control bits c3 c2 c1 c0 dac function implemented 0 0 0 0 a and b no operation (power - on default) 0 0 0 1 a load and update 0 0 1 0 a initiate readback 0 0 1 1 a load input register 0 1 0 0 b load and update 0 1 0 1 b initiate readback 0 1 1 0 b load input register 0 1 1 1 a and b update dac outputs 1 0 0 0 a and b load input registers 1 0 0 1 n/a disable daisy - chain 1 0 1 0 n/a clock data to shift register on rising edge 1 0 1 1 n/a clear dac output to zero scale 1 1 0 0 n/a clear dac output to midscale 1 1 0 1 n/a control word 1 1 1 0 n/a reserved 1 1 1 1 n/a no operation
ad5429/ad5439/ad5449 data sheet rev. e | page 22 of 28 microprocessor inter fac ing microprocessor interfacing to the ad54xx family of dacs is through a serial bus that uses standard protocol and is compatible with microcontrollers and dsp processors. the communication channel is a 3 - wire interface consisting of a clock signal, a data signal, and a synchronization signal. the ad5429/ad5439/ ad5449 require a 16 - bit word, with the default being data valid on the falling edge of sclk; however, this is changeable using the control bits in the data - word. adsp - 21xx - to - ad5429/ad5439/ad5449 i nterface the adsp - 21xx family of dsps is easily interfaced to an ad5429/ ad5439/ad5449 dac without the need for extra glue logic. figure 48 is an example of a serial peripheral interface (spi) between the dac and the adsp - 2191. t he mosi (master output, slave input) pin of the dsp drives the serial data line, sdin. sync is driven from a port line, in this case spixsel . sclk sck sync spixse l sdin mosi adsp-2191 * * additiona l pins omitted for clarit y . ad5429/ad5439/ ad5449 * 04464-027 figure 48 . adsp - 2191 spi - to - ad5429/ad5439 /ad5449 interface the adsp - 2101/adsp - 2103/adsp - 2191 processor incorporates channel synchronous serial ports (sport). a serial interface between the dac and dsp sport is shown in figure 49. in this interface example, sport0 is use d to transfer data to the dac shift register. transmission is initiated by writing a word to the tx register after sport has been enabled. in a write sequence, data is clocked out on each rising edge of the dsp serial clock and clocked into the dac input s hift register on the falling edge of its sclk. updating of the dac output takes place on the rising edge of the sync signal. sclk sclk sync tfs sdin dt adsp-2101/ adsp-2103/ adsp-2191 * * additiona l pins omitted for clarit y . 04464-028 ad5429/ad5439/ ad5449 * figure 49 . adsp - 2101/adsp - 2103/adsp - 2191 sport - to - ad5429/ad5439/ad5449 interface communication between two devices at a given clock speed is possible when the following specifications are compatible: frame sync delay and frame sync setup - and - hold, data delay and data setup - and - hold, and sc lk width. the dac interface expects a t 4 ( sync falling edge to sclk falling edge setup time) of 13 ns minimum. see the adsp - 21xx user m anual at www.analog.com for details on clock and frame sync frequencies for the sport register. table 12 shows the setup for the sport control register. table 12 . sport control register setup name setting description tfsw 1 alternate fra ming invtfs 1 active low frame signal dtype 00 right - justify data isclk 1 internal serial clock tfsr 1 frame every word itfs 1 internal framing signal slen 1111 16- bit data - word adsp - bf5xx - to - ad5429/ad5439/ad5449 interface the adsp - bf5xx famil y of processors has an spi - compatible port that enables the processor to communicate with spi - compatible devices. a serial interface between the blackfin ? processor and the ad5429/ad5439/ad5449 dac is shown in figure 50 . in this configuration, data is transferred through the mosi pin. sync is driven by the spixsel pin, which is a reconfigured programmable flag pin. sclk sck sync spixse l sdin mosi adsp-bf5xx * * additiona l pins omitted for clarit y . ad5429/ad5439/ ad5449 * 04464-033 figure 50 . adsp - bf5xx - to- ad5429/ad5439/ad544 9 interface a serial interface between the dac and the dsp sport is shown in figure 51 . when sport is enabled, initiate transmission by writing a word to the tx register. the data is clocked out on each rising edge of the dsp ser ial clock and clocked into the dac input shift register on the falling edge of its sclk. the dac output is updated by using the transmit frame synchronization (tfs) line to provide a sync signal. sclk sclk sync tfs sdin dt adsp-bf5xx* * additiona l pins omitted for clarit y . 04464-034 ad5429/ad5439/ ad5449* figure 51 . adsp - bf5xx sport - to- ad5429/ad5439/ad5449 interface
data sheet ad5429/ad5439/ad5449 rev. e | page 23 of 28 80c51/80l51 - to - ad5429/ad5439/ad5449 interface a serial interface between the dac and the 80c51/80l51 is shown in figure 52 . txd of the 80c51/80l51 drives sclk of the dac serial interface, and rxd drives the serial data line, sdin. p1.1 is a bit - programmable pin on the serial port and is used to drive sync . when data is to be transmitted to the switch, p1.1 is taken low. the 80c51/80l51 transmit data in 8 - bi t bytes only ; therefore, only eight falling clock edg es occur in the transmit cycle. to load data correctly to the dac, p1.1 is left low after the first eight bits are transmitted, and then a second write cycle is initiated to transmit the second byte of d ata. data on rxd is clocked out of the microcontroller on the rising edge of txd and is valid on the falling edge of txd. as a result, no glue logic is required between the dac and microcontroller interface. p1.1 is taken high following the completion of t his cycle. the 80c51/80l51 provide the lsb of the sbuf register as the first bit in the data stream. the dac input register requires its data with the msb as the first bit received. the transmit routine should take this requirement into account. sclk txd 80c51 * sync p1.1 sdin rxd * additiona l pins omitted for clarit y . 04464-029 ad5429/ad5439/ ad5449 * figure 52 . 80c51/80l51 - to - ad5429/ad5439/ad5449 interface mc68hc11 - to - ad5429/ad5439/ad5449 interface figure 53 is an example of a serial interface between the dac and the mc68hc11 microcontroller. the spi on the mc68hc11 is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, and clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr); see the mc68hc11 user m anual. the sck of the mc 68hc11 drives the sclk of the dac interface; the mosi output drives the serial data line (sdin) of the ad5429/ad5439/ad5449. sclk sck ad5429/ad5439/ ad5449 * sync pc7 sdin mosi mc68hc 1 1 * * additiona l pins omitted for clarit y . 04464-030 figure 53 . mch68hc11/68l11 - to - ad5429/ad5439/ad5449 interface the sync signal is derived from a port line ( pc7). when data is being transmitted to the ad5429/ad5439/ad5449, the sync line is taken low (pc7). data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11 is transmitted in 8 - bit bytes w ith only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the dac, leave pc7 low after the f irst eight bits are transferred and perform a second serial write operation to the dac. pc7 is taken high at the end of this procedure. if the user wants to verify the data previously written to the input shift register, the sdo line can be connected to miso of the mc68hc11, and, with sync low, the shift register clocks data out on the r ising edges of sclk. microwire - to - ad5429/ad5439/ad5449 interface figure 54 shows an interface between the dac and any microwire - compatible device. serial data is shifted out on the falling edge of the serial clock, sk, and is cl ocked into the dac input shift register on the rising edge of sk, which corresponds to the falling edg e of the dac sclk. sclk sk microwire * sync cs sdin so ad5429/ad5439/ ad5449 * * additiona l pins omitted for clarit y . 04464-031 figure 54 . microwire - to - ad5429/ad5439/ad5449 interface pic16c6x/7x - to - ad5429/ad5439/ad5449 interface the pi c16c6x/7x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit (ckp) = 0. this is done by writing to the synchronous serial port control register (sspcon). see the pic16/17 microcontroller user m anual for more inf ormatio n . in this example, the i/o port , ra1 , is used to provide a sync signal and enable the serial port of the dac . this micro controller transfers only eight bits of data during each serial transfer opera tion; therefore, two consecutive w rite operations are required. figure 55 shows the connection diagram. sclk sck/rc3 pic16c6x/7x * sync ra1 sdin sdi/rc4 ad5429/ad5439/ ad5449 * * additiona l pins omitted for clarit y . 04464-032 figure 55 . pic16c6x/7x - to - ad5429/ad5439/ad5449 interface
ad5429/ad5439/ad5449 data sheet rev. e | page 24 of 28 pcb layout and power supply decoupling in any circuit where accuracy is im portant, careful considera - tion of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5429/ad5439/ad5449 is mounted should be designed so that the analog and digital sections are separa te and confined to certain areas of the board. if the dac is in a system where multiple devices require an agnd - to - dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the de vice. the dac should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply , located as close as possible to the package, ideally right up against the device. the 0.1 f capacitor should have low effective series resistance (esr) and lo w effective series inductance (esi), such as the common ceramic types of capacitors that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. low esr , 1 f to 10 f tantalum or electrolyt ic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. components, such as clocks, that produce fast - switching signals , should be shielded with digital ground to avoid radiating noise to other parts of the board, and they should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this layout reduces the effects of feedthrough on the board. a micro - strip technique is by far the best method, but its use is not always possible with a double - sided board. in this technique, the compo - nent side of the board is dedicated to the ground plane, and signal traces are placed on the soldere d side. it is good practi ce to use compact, minimum lead - length pcb layout design. leads to the input should be as short as possible to minimize ir drops and stray inductance. the pcb metal traces between v ref x and r fb x should also be matched to minimize g ain error. to maximize high frequency performance, the i - to - v amplifier should be located as close as possible to the device.
data sheet ad5429/ad5439/ad5449 rev. e | page 25 of 28 overview of ad54 xx devices table 13. part no. resolution no. dacs inl (lsb) interface package 1 features ad5424 8 1 0.25 parallel ru - 16, cp -20 10 mhz bw, 17 ns cs pulse width ad5426 8 1 0.25 serial rm - 10 10 mhz bw, 50 mhz serial ad542 8 8 2 0.25 parallel ru -20 10 mhz bw, 17 ns cs pulse width ad5429 8 2 0.25 serial ru -10 10 mhz bw, 50 mhz serial ad5450 8 1 0.25 serial uj -8 10 mhz bw, 50 mhz serial ad5432 10 1 0.5 serial rm - 10 10 mhz bw, 50 mhz serial ad5433 10 1 0.5 parall el ru - 20, cp -20 10 mhz bw, 17 ns cs pulse width ad5439 10 2 0.5 serial ru - 16 10 mhz bw, 50 mhz serial ad5440 10 2 0.5 parallel ru -24 10 mhz bw, 17 ns cs pulse width ad5 451 10 1 0.25 serial uj -8 10 mhz bw, 50 mhz serial ad5443 12 1 1 serial rm - 10 10 mhz bw, 50 mhz serial ad5444 12 1 0.5 serial rm - 8 10 mhz bw, 50 mhz serial ad5415 12 2 1 serial ru -24 10 mhz bw, 50 mhz serial ad5405 12 2 1 parallel cp -40 10 mhz bw, 17 ns cs pulse width ad5445 12 2 1 parallel ru - 20, cp -20 10 mhz bw, 17 ns cs pulse width ad5447 12 2 1 parallel ru -24 10 mhz bw, 17 ns cs pulse width ad5449 12 2 1 serial ru -16 10 mhz bw, 50 mhz serial ad5452 12 1 0.5 serial uj - 8, rm -8 10 mhz bw, 50 mhz serial ad5446 14 1 1 serial rm - 8 10 mhz bw, 50 mhz serial ad5453 14 1 2 serial uj - 8, rm -8 10 mhz bw, 50 mhz serial ad5553 14 1 1 serial rm - 8 4 mhz bw, 50 mhz serial clock ad5556 14 1 1 parallel ru -28 4 mhz bw, 20 ns wr pulse width ad5555 14 2 1 serial rm - 8 4 mhz bw, 50 mhz serial clock ad5557 14 2 1 parallel ru -38 4 mhz bw, 20 ns wr pulse width ad5 543 16 1 2 serial rm - 8 4 mhz bw, 50 mhz serial clock ad5546 16 1 2 parallel ru -28 4 mhz bw, 20 ns wr pulse width ad5545 16 2 2 serial ru -16 4 mhz bw, 50 mhz serial clock ad5547 16 2 2 parallel ru -38 4 mhz bw, 20 ns wr pulse width 1 ru = tssop, cp = lfcsp, rm = ms op, uj = tsot.
ad5429/ad5439/ad5449 data sheet rev. e | page 26 of 28 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 56 . 16 - lead thin shrink small outline packa ge [tssop] (ru - 16) dimensions shown in millimeters ordering guide model 1 resolution inl (lsb) temperature range package description package option ad5429yru 8 0.5 ?40c to +125c 16 - lead tssop ru - 16 ad5429yru - reel 8 0.5 ?40c to +125c 16 - lead tss op ru - 16 ad5429yru - reel7 8 0.5 ?40c to +125c 16- lead tssop ru -16 ad5429yruz 8 0.5 ?40c to +125c 16- lead tssop ru -16 ad5429yruz - reel 8 0.5 ? 40c to +125c 16- lead tssop ru -16 ad5429yruz - reel7 8 0.5 ? 40c to +125c 16- lead tssop ru -16 ad5439yru 10 0.5 ? 40c to +125c 16- lead tssop ru -16 ad5439yru - reel 10 0.5 ? 40c to +125c 16- lead tssop ru -16 ad5439yru - reel7 10 0.5 ? 40c to +125c 16- lead tssop ru -16 ad5439yruz 10 0.5 ? 40c to +125c 16 - lead tssop ru - 16 ad5439yruz - ree l 10 0.5 ? 40c to +125c 16- lead tssop ru -16 ad5439yruz - reel7 10 0.5 ? 40c to +125c 16- lead tssop ru -16 ad5449yru 12 1 ? 40c to +125c 16 - lead tssop ru - 16 ad5449yru - reel 12 1 ? 40c to +125c 16- lead tssop ru -16 ad5449yru - reel7 12 1 ? 40c to +125c 16- lead tssop ru -16 ad5449yruz 12 1 ? 40c to +125c 16- lead tssop ru -16 ad5449yruz - reel 12 1 ? 40c to +125c 16- lead tssop ru -16 ad5449yruz - reel7 12 1 ? 40c to +125c 16- lead tssop ru -16 ev - ad54 15/ 49 sd z e valuation board 1 z = rohs compliant part.
data sheet ad5429/ad5439/ad5449 rev. e | page 27 of 28 notes
ad5429/ad5439/ad5449 data sheet rev. e | page 28 of 28 notes ? 2004 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04464 - 0 - 5/13(e)

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